With sophisticated architecture and advanced technology, KNiulink provide DDR4 IP solution with high performance and low power. In advanced process nodes, KNiulink could offer both controller and PHY IPs. In architecture, it supports Multiport AMBA AXI interface, configurable port number and support asynchronous or synchronous AXI port. For PHY interface, it will integrate DFI compatible design. O
With sophisticated architecture and advanced technology, KNiulink provide DDR3 IP solution with high performance and low power. In advanced process nodes, KNiulink could offer both controller and PHY IPs. In architecture, it supports Multiport AMBA AXI interface, configurable port number and support asynchronous or synchronous AXI port. For PHY interface, it will integrate DFI compatible design. O
With sophisticated architecture and advanced technology, KNiulink USB3.1 transceiver IP with PMA and PCS layer is designed for low power and high performance application. It is highly configurable and can be tightly integrated with the user logic or SOC resources. Data rate for Gen 1 physical layer is 5Gbps, and data rate for Gen 2 physical layer is 10Gbps.
RapidIO is a high performance, low pin count, packet switched, full duplex, system level interconnect architecture. The architecture addresses the need for faster bus speeds in an intra-system interconnect for microprocessors, digital signal processors and communications. RapidIO interconnect architecture is partitioned into a layered hierarchy of specifications which includes Logical, Common Tran
This MIPI D-PHY IP is designed to compliant with the MIPI D-PHY v1.2 specifications. It is designed for low power and high-performance application. This IP supports data rate up to 2.5Gbps.
With sophisticated architecture and advanced technology, JESD204B /204C IP with PHY and MAC layer is designed for low power and high performance application. It is fully compatible with JESD204B/204C specification, and supports link rate up to 25Gbps per lane. Take JESD204B TX IP as an example, which assembles the parallel data from the ADCs into frames and uses 8b/10b encoding, as well as optiona
The KNiulink 64G SerDes IP core supports PAM4 signaling in the range of 32.0~64.0Gbps with scrambled data. Non-return-to-zero (NRZ) signaling is supported in the range of 1.25~ 32.0 Gbps. Either scrambled or block coded (for example, 8B/10B) data is supported for 1.25 ~12.5 Gbps in NRZ mode. However, scrambled data is required for data rates greater than 12.5 Gbps. The 64G SerDes IP cores are inte
With sophisticated architecture and advanced technology, KNL 112Gbps SerDes lP with PMA and PCS layer is designed for low power and high performance application. lt is highly configurableand can be tightly integrated with the user logic or SOC and CPU resources; it can support serial data transmission protocols with link rate from 1.25Gbps to 112Gbps.
This IP is a high-speed LVDS (Low-Voltage Differential Signaling) transceiver supporting multi-channel joint. The LVDS TX & RX IP is specified for operation over the industrial temperature range. This IP operates from 3.3V/1.1V supply and works with 992Mbps data rate. It’s compatible with ANSI/TIA/EIA-644-A (LVDS) Standard.
With sophisticated architecture and advanced technology, KNiulink SATA/SAS transceiver IP with PMA and PCS layer is designed for low power and high performance application. It is highly configurable and can be tightly integrated with the user logic or SOC resources; it can support SATA protocol with data rate 1.5/3/6Gbps, and SAS protocol with data rate 1.5/3/6/12Gbps.
With sophisticated architecture and advanced technology, KNiulink multi-mode transceiver IP with PMA and PCS layer is designed for low power and high performance application. It is highly configurable and can be tightly integrated with the user logic or SOC resources; it can support a wide variety of serial data transmission protocols with link rate up to 10.3125/16/25/28/32Gbps.
基于赛昉科技RISC-V CPU IP和Interconnect Fabric IP，构建高性能、高带宽、低延迟的系统解决方案平台。
基于赛昉科技 RISC-V CPU IP 和 Interconnect Fabric IP，构建高性能、高带宽、低延迟的 RISC-V 多核系统解决方案平台。
国内首款Mesh架构一致性互联总线IP, 昉·星路-700是一款国产Mesh/Ring架构的一致性互联总线IP，支撑构建众核CPU和SoC。
StarNoC-500是赛昉科技首款自研的支持缓存一致性的Interconnect Fabric IP，支撑构建多核CPU和SoC。
昉·天枢-90 是一款支持丰富的RISC-V扩展，使能边缘、云计算和高性能计算应用的商业级64位RISC-V CPU IP。
昉·天枢-83是一款兼容RVA23 Profile, 支持Vector, Vector Crypto扩展，使能高能效应用的商业级64位RISC-V CPU IP。
昉·天枢-80是一款支持丰富的RISC-V扩展，使能高能效应用的商业级64位RISC-V CPU IP。
极低功耗的乱序商业级64位RISC-V CPU IP，专为高能效产品设计昉·天枢-70 CPU IP采用了9+级流水线、三发射、乱序执行的设计，支持丰富的RISC-V指令集RV64GCBH 。昉·天枢-70 SPEC2006int分数可达7.2/GHz， 专为高能效的计算场景而设，满足移动、桌面、人工智能的需求。经过预集成与验证，昉·天枢-70简化了SoC开发工作。昉·天枢-70提供具备内存一致性的Cluster内单核、双核及四核的配置选择，具有高度可扩展性。昉·天枢-70的能效比较同系列的昉·天枢-80高出21%。
