With sophisticated architecture and advanced technology, KNL 112Gbps SerDes lP with PMA and PCS layer is designed for low power and high performance application. lt is highly configurableand can be tightly integrated with the user logic or SOC and CPU resources; it can support serial data transmission protocols with link rate from 1.25Gbps to 112Gbps.

Deliverables

- GDSII&CDL Netlist

- Verilog Model

- LEF Layout Abstract(.LEF)

- Liberty Timing Models(.lib)

- Verify Results

- Specification

- Datasheet

- Integration Guideline

- Evaluation Plan

- Leading support for package design, SI&PI modeling and production test development

Highlights

• Highly customizable PMA configuration (controlled by PCS), X4 per Quad

• Configurable serial data, support data rate from 1.25 to 112Gbps;

• PAM4 support 56~112Gbps;

• NRZ support 1.25~56Gbps;

• Data Rate TX/RX Interface Width

• 1.25-8Gbps10bit, 16bit, 20bit, 32bit, 40bit, 64bit, 80bit, 128bit, 160bit

• 8-16Gbps16bit, 20bit, 32bit, 40bit, 64bit, 80bit, 128bit, 160bit

• 16-56Gbps 32bit, 40bit, 64bit, 80bit, 128bit, 160bit

• 56-112Gbps64bit, 80bit, 128bit, 160bit

• Two cascaded PLLs, one LC-tank based and the other ring-oscillator based

• Digitally-control-impedance termination resistors

• Configurable TX output differential voltage swing

• Built-in TX De-Emphasis

• RX Built-in CTLE with programmable boost

• Support Forward Clock Mode/Common Clock/CDR Assist mode

• PLL Frequency Lock detection

• Multiple Loop Back, BIST, and Analog DC Testing

• Support RX Built-in Eye Opening Monitor

• Reference clock repeater for other Quads

• Support Boundary Scan Interface for Serial link, compliant with IEEE 1149.6-2003/ 1149.1-2001

• BIST generator and checker

• Support data polarity inversion

• TX/RX status control

• Provide the corresponding interface clocks to external SOC

• Power on/reset sequence control

• Support DFT

• JTAG/APB control register access interface

• Supports Flip-Chip package